000			00561cam a2200181ua 4500
001			2192
008			120919n2003 ii |||gr||||Z||||||eng
020			_a9788131508763
040			_aIN-GwRGU
082			_a621.381
100	1		_a Lee, Sunggu,. _eAuthor.,
245	0	0	_aDigital Logic Design : : _bUsing Verilog, State Machines and Synthesis for FPGAs / / _cBy Sunggu Lee . .
250			_a1st ed.
260			_aNew Delhi _bCengage Learning _c2003
300			_a320p.: _c24 cm.
650			_aDigital Logic Design1 _aElectronics & Telecommunications
942			_2ddc _cBK
999			_c2043 _d2043