Uyemura,  John P, <br/><br/>
Chip Design for Submicron VLSI:  CMOS layout and simulation /  
By John P. Uyemura .  
 - 1st ed. 
 - New Delhi  Cengage Learning  2006 
 - xvi, 411 p.:  24 cm. 
<br/><br/><label>ISBN: </label>9788131501955 8131501957 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Chip Design for Submicron VLS
<br/><br/><label>Dewey Class. No.: </label>621.395