Digital Logic Design : : (Record no. 2043)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00561cam a2200181ua 4500 |
| 001 - CONTROL NUMBER | |
| control field | 2192 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 120919n2003 ii |||gr||||Z||||||eng |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9788131508763 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | IN-GwRGU |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.381 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Lee, Sunggu,. |
| Relator term | Author., |
| 245 00 - TITLE STATEMENT | |
| Title | Digital Logic Design : : |
| Remainder of title | Using Verilog, State Machines and Synthesis for FPGAs / / |
| Statement of responsibility, etc. | By Sunggu Lee . . |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Cengage Learning |
| Date of publication, distribution, etc. | 2003 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 320p.: |
| Dimensions | 24 cm. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Digital Logic Design1 |
| -- | Electronics & Telecommunications |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total checkouts | Full call number | Barcode | Date last seen | Copy number | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RGU Central Library | RGU Central Library | Ground Floor Stack | 01/02/2024 | 621.381 | LEE | 9422 | 01/02/2024 | 1 | 01/02/2024 | Books |
